1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the fabrication of low-k interlayer dielectric layers on a substrate.
2. Description of the Related Art
Semiconductor devices typically include device components (such as transistors and capacitors) that are formed on or in a substrate as part of the front end of line (FEOL) processing. In addition, interconnect features (such as contacts, metal lines and vias) that connect the device components to the outside world are included as part of the back end of line (BEOL) integration process whereby one or more dielectric layers are formed in and between the interconnect features for purposes of electrically isolating the interconnect features and device components. But as geometries in microelectronic devices continue to shrink in size, the RC delay and crosstalk effects caused by the more densely packed interconnect features have increased. In response, low dielectric constant (low-k) dielectric layers (e.g., materials having a relative permittivity or dielectric constant that is typically less than four) are increasingly used to isolate the interconnect and metallization features from the underlying device components in order to minimize RC delay and crosstalk. In addition, multi-layered interconnection structures are increasingly used to improve device reliability, where each interconnection layer is formed in a planar fashion.
In this area, dual damascene processes have been developed for fabricating low-k interlayer dielectric structures, such as described at U.S. Pat. No. 7,183,195 and U.S. Pat. No. 7,199,474. However, in these conventional dual damascene fabrication processes, the depth of the trench opening is controlled by etch time when the etch rate is assumed to be stable, but the actual etch rate can be sensitive to many factors, such as chamber condition and the property of the material being etched. For example, FIG. 1 depicts a partial cross-sectional view of a conventional hybrid dielectric structure formed with two different dielectric layers 12, 13 that are disposed over a substrate 1, where the first or via level layer 12 is formed with a higher dielectric constant material having a lower etch rate, and the second or trench level layer 13 is formed with lower dielectric constant material having a higher etch rate. The etch selectivity between the different materials in the layers 12, 13 provides the endpoint signal and trench depth control when forming the trench opening 14. However, a drawback of this scheme is the higher total capacitance and the introduction of an additional interface between the first and second dielectric layers 12, 13 which could become a reliability concern. Another example of a conventional hybrid dielectric structure is shown in FIG. 2 which depicts a partial cross-sectional view of a hybrid dielectric structure in which an intervening etch stop layer 16 is formed between two different dielectric layers 15, 17 formed over a substrate 1. Typically, the etch stop layer 16 is formed with a higher dielectric constant material having a lower etch rate, which can improve the trench etch control and the total capacitance as compared to the hybrid dielectric structure of FIG. 1, but at the expense of adding additional interfaces which can further worsen reliability problems.
Accordingly, a need exists for an improved interlayer dielectric structures and processes for fabricating same with improved process control, less variation in trench depth variation, reduced yield loss, and/or improved device performance to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.